64 core cpu from intel

Practical and theoretical implementation discussion.
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Re: 64 core cpu from intel

Post by hobold » Mon Nov 25, 2013 11:38 am

Some more information has cropped up:

http://vr-zone.com/articles/xeon-phi-kn ... 64112.html

Apparently Knights Landing will use a derivative of the Silvermont (Atom) core. The above report speaks about "two 512b vector units per core", but it is still unclear if that means two floating point multiply-add pipelines, or a combination of one FP and one fixed point unit.

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Re: 64 core cpu from intel

Post by hobold » Tue Dec 03, 2013 10:29 pm

Latest details about Knights Landing as reported by c't magazin:

The modified cores have two parallel SIMD FPUs; theoretical peak throughput is two 512 bit wide fused multiply adds per clock, that means 64 single precision FLOPs or 32 double precision FLOPs per clock cycle.

The issue width is still two instructions per clock. That implies it will be very difficult to fully saturate both vector FPUs for any significant amount of time. (Memory accesses and integer instructions compete with floating point instructions.)

Clock speed is expected to be similar to current Xeon Phi: somewhere near 1.3GHz.

Cores are paired, with each pair sharing a level 2 cache.

There is no ring bus anymore. The cores are organized in a 2D mesh.

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Re: 64 core cpu from intel

Post by Geri » Tue Dec 03, 2013 11:48 pm

well yeah, integer is better, however, i know why we using fpu-s, but i cant speak so good english to tell the whole story .D
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soren renner
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Re: 64 core cpu from intel

Post by soren renner » Wed Dec 11, 2013 3:59 pm

hobold wrote:
beason wrote: Of course, there is still the classical challenge of coming up with multithreaded algorithms that scale so high, while producing actual results rather than just excess heat. :-)
Done. See viewtopic.php?f=5&t=1905

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