Dade wrote:Xeon Phi cores are _lot_ slower than today average Xeon cores, I assume that the performance will be awful if you don't use (directly or by OpenCL) the new AVX instructions.
Indeed they are slow. Microprocessor experts outside Intel are currently puzzled how the future chip can hit the announced 3 TFLOPS double precision. This is more than double the throughput of current Larrabee chips, so either clock frequency would have to rise from a little over 1GHz to 2.3GHz. Or vector width would have to double from 512 bits to 1024 bits (with only a modest frequency boost).
Doubled clocks are deemed unlikely, because that would destroy FLOPs/Watt efficiency. Doubled vector width is deemed unlikely as well, because Intel info specifically talks about AVX-512. Another alternative is two independent vector FPUs per core, but that is deemed unlikely because a dual issue pipeline would be woefully inadequate to saturate both (there are memory accesses, address computations, loop overhead, etc. to compete with FPU instructions). The final alternative would be significantly more powerful cores (3-wide out of order execution, etc.), but there simply is no processor core anywhere on Intel's roadmap that would meet the required balance of power consumption, performance, and silicon area.
The only thing that is known for certain today is that there is more to Knights Landing than meets the eye. Interesting times, as usual.
